Integrated circuits are formed from semiconductor substrates, usually silicon (Si), within and upon whose surfaces are formed active semiconductor regions containing electrical circuit elements that are internally and externally connected to the substrate through multiple patterned conductor layers that are separated by dielectric layers. These active semiconductor regions must be otherwise electrically isolated from adjacent active semiconductor regions by the formation of intervening trenches which are subsequently filed with dielectric material to ensure such electrical isolation and avoid undesired interference between adjacent active semiconductor regions. The continued miniaturization of integrated circuit devices has resulted in smaller trenches formed by, for example, shallow trench isolation (STI) methods to form trench isolation regions essentially co-planar with adjacent active semiconductor regions of the semiconductor substrates.
One approach to reducing undesired stray capacitance has been to use silicon-on-insulator (SOI) substrates. This allows higher operating frequencies, better packing density, borderless contacts, latch-up freedom, and radiation hardness. However, junction leakage and capacitance are still too high for newer applications and the wafer cost to form typical SOI transistors is very high.
U.S. Pat. No. 5,712,173 to Liu et al. describes a method of forming a semiconductor device having the advantages of a silicon on insulator structure by implanting oxygen ions using the gate electrode as a mask and then heating to form thin, self-aligned buried oxide regions extending from a field oxide region under source/drain regions and self-aligned with the side surfaces of the gate electrode. In an alternate embodiment, the buried oxide layer extends from a point proximate the field oxide region and/or partially under the gate electrode.
U.S. Pat. No. 4,506,435 to Pliskin et al. describes first lining the trench with a silicon oxide lining then filling the trench with, for example, a borosilicate glass. The borosilicate glass layer is heated, causing it to soften and flow to approach planarity. Then the borosilicate glass layer and SiN mask layer are etched to make the borosilicate glass filled trench substantially planar with the SiO masking layer.
U.S. Pat. No. 5,882,958 to Wanlass describes a method of producing silicon-on-insulator (SOI) metal-oxide semiconductors (MOS) by damascene patterning of source-drain regions in a thin film of amorphous silicon deposited on a layer of oxide grown on a silicon wafer, where the oxide has previously been etched with a pattern of trenches. The method provides for the amorphous layer to contact the underlying silicon substrate through multiple small oxide openings, where subsequent transistor channel regions will align to these openings.
U.S. Pat. No. 5,891,763 to Wanlass describes a process for producing planar silicon-on-insulator MOS transistors having a polysilicon gate. The channel regions are created in an underlying single crystal silicon wafer, and the source-drain extensions regions are created by damascene patterning a thin film of amorphous silicon deposited on a layer of oxide deposited on the silicon wafer.
U.S. Pat. No. 5,869,359 to Pabhakar describes a method of producing silicon-on-insulator devices having elevated source and drains and a polysilicon gate. The silicon-on-insulator oxide is only under the source/drain regions and not under the channel. Greater control over the channel length is achieved.
U.S. Pat. Nos. 5,610,087 and 5,728,613, both to Hsu et al., each describe methods in which narrow base width, lateral bipolar junction transistors (BJT), and short channel length metal-oxide semiconductor field-effect transistor (MOSFET) devices can be simultaneously fabricated in a silicon-on-insulator (SOI) layer.
U.S. Pat. No. 5,445,107 to Roth et al. describes a method of forming a semiconductor device from a silicon-on-insulator film formed by solid phase epitaxial re-growth. A layer of amorphous silicon is formed such that it is only in direct contact with an underlying portion of a silicon substrate. The layer of amorphous silicon is subsequently annealed to form a monocrystalline layer of epitaxial-silicon having a low density of crystal defects since the layer of amorphous silicon is only in contact with an underlying portion of a silicon substrate allowing uniform epitaxial re-growth.
U.S. Pat. No. 5,612,230 to Yuzurihara et al. describes a process for forming a semiconductor device by applying a non-single-crystalline material on a sidewall inside of an opening portion for growing a single-crystalline semiconductor body.
U.S. Pat. No. 4,749,441 to Christenson et al. describes a method of fabricating single crystal silicon in a "mushroom" shape to use in fabricating devices such as a silicon-on-insulator-like MOSFET.
U.S. Pat. No. 5,686,343 to Lee describes a method for the isolation of a semiconductor layer on an insulator. A window is formed within a first insulating layer which becomes an epitaxial growth seed; a semiconductor layer is deposited and an epitaxial layer having the same crystal structure as the semiconductor substrate under the window is grown; an active area of the epitaxial layer is formed by a photolithographic process; a second insulation layer on and at the side of the active area and on the first insulating layer is formed; and an active area is isolated from the semiconductor layer by forming a third insulator layer in the window by an oxidation process.